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Job Information
Job title

Layout Engineer

Company Qimonda
Wage between $0.00 - $0.00 Annually
Location United States, Vermont, Williston
Employment type Full Time
Education Bachelor
Year Experience 2 - 3 Years of Practical Experience
Travel None
Published on 3/15/2007
Description
DESCRIPTION:
The DRAM Design/Layout Engineer's main functions are but are not limited to:

Support design teams to convert the schematic description into optimized floorplanning and topology as well as structured block layout for state of the art low power DRAM's
Work closely with the Design Team to complete a variety of physical design assignments that meet the requirements of the engineered schematics and physical design rule criteria, including the verification of the layout with standard tools (LVS, DRC)
Focus is on full custom physical design from global floor planning to individual circuit block layout (analog and digital design blocks)


REQUIREMENTS:
In accomplishing this task, the engineer must have the following skills:



Bachelor's or equivalent technical industry experience in full custom layout is required
At least 3 years of experience in transistor level full custom layout and floorplanning
Experience with DRAM, SRAM and/or Pseudo-SRAM design and CMOS IC mask design methodologies is a plus
Familiar with operating standard DRC and LVS tools (Cadence, Mentor Graphics) and good problem solving skills


QUALIFICATIONS:

Engineer 1: MSEE or BSEE with no industry experience
Engineer 2: MS + 1 year experience or BS + 6 years experience
Senior Engineer: MS + 2 years experience or BS + 7 years experience
Staff Engineer: MS + 5 years experience or BS + 10 years experience
Senior Staff Engineer: MS + 7 years experience or BS + 12 years experience
Principal: MS + 10 years experience or BS + 15 years experiencedf-tc

Experience/Skills
See above

Other desired skills:
Layout Engineer
This job has expired.