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Job Information
Job title

Lead IC Verification Engineer for SiRF

Company Pyramid Screening Technology
Wage between $0.00 - $0.00 Hourly
Location United States, California, San Jose
Employment type Full Time
Education Not Specified
Year Experience 4 - 5 Years of Practical Experience
Travel None
Published on 8/6/2004
Description
SiRF was founded in March 1995 and uses the fab-less semiconductor model for our products. We currently employ about 160 persons split between our San Jose, South San Francisco, Irvine and Cedar Rapids offices. More than 70% of our staff is committed to research, development and customer engineering.

SiRF Technology Inc. develops and markets semiconductor and software products designed to enable location awareness in high-volume mobile consumer devices and commercial applications. Location awareness refers to the ability of a device to determine and make use of the information regarding its location.

SiRF's products enable a range of devices to utilize GPS to detect location. They have been integrated into mobile consumer devices, such as automobile navigation systems, cellular phones, GPS-based mobile computing peripherals and handheld GPS navigation devices, as well as into commercial applications, such as property tracking devices and fleet management systems.

SiRF markets and sells its products in four target markets: wireless handheld, automotive, mobile computing and embedded consumer applications.

Lead IC Verification Engineer

Location: San Jose, CA 95112

Responsibilities
. Develop, implement, and enhance IC verification environment and methodology for GPS signal processing engine.
. Provide leadership in verification planning and managing the verification process.
. Develop and document test plans that identify all test cases required to validate the design (what needs to be checked, how to check and why it needs to be checked)
. Architect testbenches that identify the self-checking components needed, the model requirements for input drivers & golden output models, and the mechanism for automating test case generation
. Implement/debug testbenches in a high level verification language at a high level of abstraction transaction level if appropriate)
. Generate/debug test cases and work with designers in debugging any design related issue
. Provide assistance to designers writing assertions and creating module level test environments with reusable components
. Explore advance verification concepts/methodologies/tools like functional coverage, formal verification
. Maintain a document of the existing methodology
. Manage regression runs and automate regression by writing appropriate scripts
. Track test generation activities and progress of RTL and gate level debugging activities
. Provide coverage analysis (code, functional)
. Coordinate with chip validation team (Systems, FPGA, bring-up) in maintaining the known golden set of test vectors.

. Must be well versed in multiple verification environments (Cadence, Synopsys, Mentor Graphics) in either Unix or Linux
. Must possess good communication skills and the ability to work well in a team.
. Must have experience as a lead verification engineer doing both technical hands on work as well as co-coordinating verification tasks.
. Minimum of 5 years experience in complex ASIC verification and/or ASIC design.
. BS in Electrical Engineering, MS preferred

. Minimum of 5 years experience in complex ASIC verification and/or ASIC design.
. BS in Electrical Engineering, MS preferred


SiRF offers competitive salaries and benefits and a generous incentive stock option plan. Our working environment is relaxed and informal.

If you are interested in joining a fast-growing startup and have experience in GPS, spread spectrum, semiconductor or wireless technologies, please consider SiRF.



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Experience/Skills
. Must be strong in Verilog, C, and scripting (Perl, Awk, shell).
. Must have some knowledge of a High Level Verification language (SystemC or SystemVerilog)
. Must have experience in writing assertions in either Verilog, OVL, PSL or SystemVerilog
. Must have good knowledge of Embedded Systems with some experience in low level assembly language (ARM based is preferred)
. Must have solid understanding of digital logic and have some knowledge of GPS or DSP based systems.

Other desired skills:
. Must be strong in Verilog, C, and scripting (Perl, Awk, shell).
. Must have some knowledge of a High Level Verification language (SystemC or SystemVerilog)
. Must have experience in writing assertions in either Verilog, OVL, PSL or SystemVerilog<
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