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Job Information
Job title

Senior Principal Systems Design Engineer -

Company At-Tech
Wage between $0.00 - $0.00 Annually
Location United States, California, Irvine
Employment type Full Time
Education Not Specified
Year Experience 4 - 5 Years of Practical Experience
Travel Not Specified
Published on 10/6/2008
Description
My client is seeking an experienced Senior Principal Systems Design Engineer to help develop Ethernet networking transceiver architectures spearheading company's expansion in the Ethernet PHY communication semiconductor market.

Join a world-class design team, work with the other industry leading architects and design engineers to deliver signal processing modules of multi-gigabit Ethernet ASICs for low power, low cost and cutting-edge performance.

This system designer/architect will be a key member of a team of highly competent system engineers involved in research, design, simulation, and implementation (ASIC) of advanced signal processing
algorithms for the physical layer of high speed wired data communication networks. The types of algorithms that will be designed/refined include: PAM/QAM base band modems, single/multi-input adaptive pre-coders/equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions. The candidate will have a senior role on a team with responsibilities including:
- Investigation, analysis, and development of advanced signal processing and communications algorithms for Ethernet transceivers
- MATLAB and C/C++ system modeling and simulation
- Defining system specifications
- ASIC architecture definition and direction of implementation activities
- System level verification of RTL hardware implementations
- Lab testing/debug of ASICs and complete consumer products
- Documentation/application note development and customer support

REQUIREMENTS:
MSEE/PhD EE.
8+ years experience developing, implementing, and testing communications and DSP algorithms targeted for ASIC implementation.
Extensive experience in MATLAB and C/C++ based system simulation and evaluation.
Experience in mapping communications algorithms to hardware and debug/test experience using analog and digital bench equipment.
Must have experience architecting communication systems for high performance ASIC based products.
Experience in RTL design, simulation, and synthesis a plus. Knowledge of gigabit and/or 10 gigabit physical layer architectures a plus.
Should have strong presentation and writing skills.df-tc

Experience/Skills
, , MSEE/PhD EE.
8+ years experience developing, implementing, and testing communications and DSP algorithms targeted for ASIC implementation.
Extensive experience in MATLAB and C/C++ based system simulation and evaluation.

Other desired skills:
, , MSEE/PhD EE. 8+ years experience developing, implementing, and testing communications and DSP algorithms targeted for ASIC implementation. Extensive experience in MATLAB and C/C++ based system simulation and evaluation.